1. Field of the Invention
The present invention relates to a method for processing a high-k (high dielectric constant) dielectric layer and more particularly, to an annealing process for processing a high-k dielectric layer.
2. Description of the Prior Art
With a trend towards scaling down the size of metal-oxide-semiconductors (MOS), the thickness of a gate dielectric layer must be reduced; if the gate dielectric layer is insufficient for sustaining a breakdown voltage, however, the phenomenon of serious leakage current will occur. Additionally, boron penetration from the polysilicon gate results in a deterioration of the device performance. Therefore, the semiconductor industry tends to use metal gates and high-K (high dielectric constant) materials to replace the conventional polysilicon gate and silicon oxide gate dielectric layer.
An annealing process is further implemented for improving the quality of gate dielectric layer formed through the atomic layer deposition (ALD) process or other processes. The gate dielectric layer made of oxide and the gate dielectric layer made of high-k materials are different; accordingly, as the annealing processes applicable for the gate dielectric layer made of oxide are used to process the gate dielectric layer made of high-k materials, the temperature profiles of the temperature controllers in the process tool may disperse. In other words, the consistency of the temperature controller performance is lost. This will adversely impact the process stability, and in a worst-case scenario, cause the wafer to be broken. How to establish an annealing process suitable for improving the quality and the reliability of high-k dielectric layer is therefore still an important issue in the field.